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Biomimetic MicroElectronic Systems
Engineering Research Center
University of Southern California

1450 San Pablo Street
DVRC - 130
Los Angeles, CA 90033

T. 323-442-6786
F. 323-442-6790

Mixed-Signal Systems on Chip (M-S SoC) Thrust
Led by John G. Granacki, Ph.D.

Biomimetic microelectronic systems require novel engineering approaches to deliver devices that can be integrated and functional with tissue. These systems must be small, biocompatible, power efficient, and computationally fast. We are developing mixed-signal VLSI device technology to enable that will allow the realization of these goals.[i] Device size and power is being reduced by exploiting the commercial technology, particularly processes for fabricating digital devices, which shrinks feature size every three years. This size reduction in turn allows single-chip neural implants to replace multi-chip.

  • Demonstrated VlSI "CA3 replacement" for rat brain hippocampal slice<br>- 0.18 micon CMOS<br>- 1.22 mm x 1.22 mm(core)
  1. 0.18 micron CMOS
  2. 1.22 mm x 1.22 mm (core)
  3. 65 K gates
  4. ~2 mW
  5. 120 MOPs (24 bits)
  • Fabricated by MOSIS(Taiwan Semiconductor Manufacturing Company


 

 


[1] Wentai Liu, Mohanasankar Sivaprakasam, Guoxing Wang, Mingcui Zhou, John Granacki, Jeff LaCoss and Jack Wills, "Implantable Biomimetic Microelectronic Systems Design, IEEE Engineering in Medicine and Biology Magazine, Volume 24, Number 5, September/October 2005.
 
At a system level, the Mixed-Signal Systems on a Chip Technology Thrust has completed a full set of experiments with the Cortical Testbed on a rat brain slice in vitro and has achieved excellent agreement between the VLSI implementations and the biological CA3 slice response. The second prototype of the single channel VLSI chip was fabricated through MOSIS in TSMC’s 0.18 micron CMOS. This fully tested VLSI implementation includes the real time spike detection circuit and occupies only approximately 1.5 square mm of die area. The VLSI device contains 65K gates and at a clock speed of 5.5 MHz consumes ~2 milliwatts with a throughput of 120 MOPs (24 bits). This result implies that we could integrate 50-100 channels on a single chip. We have also submitted a chip to fabrication that includes the analog processing and Analog-to-Digital Converter integrated together with the digital single-channel model. At a more fundamental research level, we are currently testing a novel charge-metering stimulation amplifier design with the retinal testbed. We are also working with our industrial partners from Texas Instrument to develop Current Mode Logic libraries to further lower the power dissipation of the VLSI design.